1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a structure having a semiconductor growth layer on an insulation layer.
2. Description of the Prior Art
In a semiconductor integrated circuit, an epitaxial growth layer is generally formed on a silicon substrate, and devices are formed on the epitaxial growth layer. In this structure, however, a p-n junction is formed in the interface of the silicon substrate and the epitaxial growth layer, so that parasitic capacitance arises. The parasitic capacitance causes the operating speed of the devices to be reduced. Consequently, the above-described structure is not suitable for the formation of devices requiring a high-speed operation.
In order to solve this problem, it has been desired in recent years to develop the SOI (Semiconductor-On-Insulator) technique for forming an insulation layer on a silicon substrate and further forming a single-crystalline silicon layer on the insulation layer. This technique is an attempt to prevent a p-n junction from being formed between the single-crystalline silicon layer and the silicon substrate by insulating the single-crystalline silicon layer from the silicon substrate.
FIG. 11 illustrates the conventional SOI technique using the ELO (Epitaxial Lateral Overgrowth) process (see an article by D. D. Rathman et al, entitled "Lateral Epitaxial Overgrowth of Silicon on SiO.sub.2 ", JOURNAL OF ELECTRO-CHEMICAL SOCIETY SOLID-STATE SCIENCE AND TECHNOLOGY, October 1982, p. 2303).
First, a silicon oxide film 3 is grown on the surface of a semiconductor substrate 1. The silicon oxide film 3 is then selectively etched using a photoresist, to open seed windows 5 (see FIG. 11 (a)). In addition, selective epitaxial growth of silicon is made in the longitudinal direction from each of the seed windows 5. Subsequently, epitaxial growth in the lateral direction is made, to form an epitaxial layer 7 on the silicon oxide film 3 (see FIG. 11 (b)). In such a manner, the area of a p-n junction between the epitaxial layer 7 and the silicon substrate 1 can be decreased to the size of the seed window 5. Consequently, the capacitance of the p-n junction can be decreased, thereby to make it possible to operate devices at higher speed.
In this ELO process, however, the p-n junction is not completely prevented from being formed, although the area of the p-n junction is decreased. That is, in the seed window 5, the formation of the p-n junction is unavoidable. Consequently, it is difficult to obtain an SOI structure having a large area on the silicon substrate, and the devices are prevented from being operated at still higher speed.
On the other hand, other methods for obtaining an SOI structure include a method referred to as the SENTAXY process (see an article by T. Yonehara et al, entitled "New SOI-Selective Nucleation Epitaxy, Proceedings of 48-th Conference on Applied Physics, 1987 (Autumn), 19p-Q-15, p. 583). This is a method of artificially forming a plurality of silicon nuclei for crystal growth on an insulation layer such as a silicon oxide film and making epitaxial growth from the respective nuclei. A method of forming a silicon nitride film having a very small area as a nucleus and using the same, a method of forming nuclei using the FIB (Focused Ion Beam) process, and the like have been examined.
According to this method, an epitaxial layer and a silicon substrate can be completely insulated from each other by the insulation layer such as the oxide film, thereby to make it possible to solve the above-described problem due to the capacitance of the p-n junction.
In this SENTAXY process, however, a new problem arises that parts of the epitaxial layer respectively grown from the plurality of nuclei differ from each other in surface direction. If the parts of the epitaxial layer grown from the respective silicon nuclei differ from each other in surface direction, characteristics such as an oxidation rate vary in the respective parts of the epitaxial layer. As a result, there arises a problem that the characteristics of devices formed on the respective parts of the epitaxial layer cannot be made equal.
3. Description of the Related Art
Therefore, the applicant of the present application has proposed manufacturing methods shown in FIGS. 9 and 10 as a method of manufacturing a semiconductor device having a silicon growth layer which is completely insulated from a substrate by an insulation layer and is uniform in surface direction.
In the manufacturing method shown in FIG. 9, a silicon oxide layer 4 is first formed on a silicon substrate 2 (see FIG. 9 (a)). Openings 14 are then formed in this silicon oxide layer 4 (see FIG. 9 (d)). Silicon is grown until it is slightly projected from each of the openings 14, to form a seed crystalline silicon layer 16 (see FIG. 9 (e)). Thereafter, a nitride film 18 is formed on the surface of the seed crystalline silicon layer 16, followed by oxidation (see FIG. 9 (g)). Consequently, field oxide layers 20 are coupled to each other in the bottom part of the opening 14, so that the seed crystalline silicon layer 16 is insulated from the silicon substrate 2 (see FIG. 9 (h)). Thereafter, epitaxial growth is made from the seed crystalline silicon layer 16, to obtain a silicon growth layer 21 (see FIG. 9 (i)). Devices are formed on the growth layer 21.
On the other hand, in the manufacturing method shown in FIG. 10, a silicon oxide layer 4 is first formed on a silicon substrate 2 (see FIG. 10 (a)). Openings 14 are then formed in this silicon oxide layer 4 (see FIG. 10 (d)). Silicon carbide is grown until it is projected from each of the openings 14, to form a seed crystalline silicon carbide layer 17 (see FIG. 10 (e)), followed by oxidation. Consequently, field oxide layers 20 are coupled to each other in the lower part of the opening 14, so that the seed crystalline silicon carbide layer 17 is insulated from the silicon substrate 2 (see FIG. 10 (f)). Thereafter, epitaxial growth is made from the seed crystalline silicon carbide layer 17, to obtain a silicon carbide growth layer 22 (see FIG. 10 (h)). Devices are formed on the growth layer 22.
According to the above-described manufacturing methods, the growth layers 21 and 22 having no p-n junction between the silicon substrate 2 and the same can be obtained, as respectively shown in FIGS. 9 (i) and 10 (h). Moreover, both the seed crystalline layers 16 and 17 each formed on the respective parts of the silicon substrate 2 are single crystals each grown using the surface of the silicon substrate 2 as a seed crystal. Therefore, the growth layers 21 and 22 grown from the respective seed crystalline layers 16 and 17 each formed on the substrate 2 can be uniform in surface direction.
In each of the above described manufacturing methods, however, it is necessary to grow the silicon oxide layer 4 in the lateral direction to close the openings 14. Accordingly, the width or the diameter of the opening 14 must be, for example, not more than 2 .mu.m, that is, the size of the opening 14 cannot be made too large.
Stacking faults are liable to occur in the interface of the opening 14 and the seed crystalline layer 16 or 17. Accordingly, the percentage of a crystal in the central part, where there are few stacking faults, of the seed crystalline layer 16 or 17 grown from the small opening 14 is low. That is, it is difficult to obtain the seed crystalline layers 16 and 17 having high crystallinity. As a result, the crystallinity of the growth layers 21 and 22 becomes low.
Furthermore, the width or the diameter of the opening 14 is limited to not more than 2 .mu.m. Accordingly, the seed crystalline layer 16 or 17 cannot be formed to have a very large area. Therefore, a long time is required to epitaxially grow the seed crystalline layers 16 and 17 to obtain the growth layers 21 and 22 having a required area.